Elpida leverages architecture to achieve chip shrink

Elpida’s chip size shrink was made possible by leveraging a new architecture on first-generation 65-nm process products, and estimates that costs for the shrunken version of 65-nm products will be approximately 20% less compared to first-generation products, the company explained. By Ann Steffora Mutschler, Senior Editor -- Electronic News, 10/6/2008 By using a new architecture on first-generation 65-nm process products, Tokyo-based DRAM giant Elpida Memory Inc said today it has developed a shrunken version of its 1-gigabit DDR2 SDRAM that is meant to deliver 20% more chips from a single 300-mm wafer, which translates to a 60% increase in chips compared with wafers for a 70-nm process, with volume production to begin before the end of this year. Production will be shared between its Hiroshima Plant, its Taiwan-based Rexchip... [read full story]